ispEXPERT Compiler Release 8.0.51.2, Dec 16 1999 10:55:54 Design Parameters ----------------- EFFORT: HIGH (3) IGNORE_FIXED_PIN: OFF MAX_GLB_IN: 16 MAX_GLB_OUT: 4 OS_VERSION: Windows 95 PARAM_FILE: _and_ff PIN_FILE: and_ff.xpn STRATEGY: DELAY TIMING_ANALYZER: FREQUENCY SETUP_HOLD CLOCK_TO_OUTPUT PRIMARY_IN_TO_OUT USE_GLOBAL_RESET: ON XOR: OFF Design Specification -------------------- Design: and_ff Part: ispLSI1016E-80LJ44 ISP: ON ISP_EXCEPT_Y2: OFF PULL: UP SECURITY: OFF Y1_AS_RESET: ON SLOWSLEW: OFF Number of Critical Pins: 1 Number of Free Pins: 0 Number of Locked Pins: 11 Number of Reserved Pins: 0 Input Pins Pin Name Pin Attribute CKIO LOCK 11 DOUT LOCK 42, PULLUP FS LOCK 44, PULLUP IORES LOCK 2, PULLUP SCK0 LOCK 3, PULLUP SCLK LOCK 41, PULLUP TXD0 LOCK 4, PULLUP Output Pins Pin Name Pin Attribute DIN LOCK 43, PULLUP IRQ0 LOCK 6, PULLUP MCLK CRIT, LOCK 40, PULLUP RXD0 LOCK 5, PULLUP Pre-Route Design Statistics --------------------------- Number of Macrocells: 30 Number of GLBs: 10 Number of I/Os: 10 Number of Nets: 34 Number of Free Inputs: 0 Number of Free Outputs: 0 Number of Free Three-States: 0 Number of Free Bidi's: 0 Number of Locked Input IOCs: 5 Number of Locked DIs: 1 Number of Locked Outputs: 4 Number of Locked Three-States: 0 Number of Locked Bidi's: 0 Number of CRIT Outputs: 1 Number of Global OEs: 0 Number of External Clocks: 1 GLB Utilization (Out of 16): 62% I/O Utilization (Out of 33): 30% Net Utilization (Out of 97): 35% Nets with Fanout of 1: 26 Nets with Fanout of 2: 6 Nets with Fanout of 3: 2 Average Fanout per Net: 1.29 GLBs with 1 Input(s): 1 GLBs with 2 Input(s): 1 GLBs with 3 Input(s): 1 GLBs with 4 Input(s): 4 GLBs with 5 Input(s): 1 GLBs with 6 Input(s): 1 GLBs with 7 Input(s): 1 Average Inputs per GLB: 4.00 GLBs with 1 Output(s): 3 GLBs with 3 Output(s): 1 GLBs with 4 Output(s): 6 Average Outputs per GLB: 3.00 Number of GLB Registers: 25 Number of IOC Registers: 0 Post-Route Design Implementation -------------------------------- Number of Macrocells: 30 Number of GLBs: 10 Number of IOCs: 9 Number of DIs: 1 Number of GLB Levels: 2 Clock GLB glb00, B0 4 Input(s) (glb07.O0, N_46_Q_BLIF, I12), (glb03.O0, N_90_Q_BLIF, I3), (SCK0.O, SCK0X, I7), (SCLK.O, SCLKX, I11) 3 Output(s) (N_47_Q_BLIF, O2), (N_47_C, O1), (BUF_802, O0) 4 Product Term(s) Output N_47_Q_BLIF 1 Input(s) N_46_Q_BLIF 2 Fanout(s) RXD0.IR, DIN.IR 1 Product Term(s) 1 GLB Level(s) N_47_Q_BLIF.D = N_46_Q_BLIF N_47_Q_BLIF.C = N_47_C N_47_Q_BLIF.R = Output N_47_C 3 Input(s) SCLKX, N_90_Q_BLIF, SCK0X 5 Fanout(s) glb09.CLK2, glb08.CLK2, glb07.CLK2, glb00.CLK2, glb02.CLK2 2 Product Term(s) 1 GLB Level(s) N_47_C = !SCK0X # N_90_Q_BLIF & SCLKX Output BUF_802 1 Input(s) SCLKX 2 Fanout(s) glb06.CLK1, glb05.CLK1 1 Product Term(s) 1 GLB Level(s) BUF_802 = SCLKX GLB glb01, B1 5 Input(s) (glb01.O1, MCLK_Q_BLIF, I16), (glb06.O0, N_91_Q_BLIF, I11), (glb04.O0, N_98_Q_BLIF, I15), (FS.O, FSX, I8), (IORES.O, IORESX, I17) 4 Output(s) (MCLK_Q_BLIF, O1), (AND_798, O3), (AND_780, O0), (AND_779, O2) 4 Product Term(s) Output MCLK_Q_BLIF 2 Input(s) N_98_Q_BLIF, MCLK_Q_BLIF 2 Fanout(s) glb01.I16, MCLK.ID 2 Product Term(s) 1 GLB Level(s) MCLK_Q_BLIF.D = N_98_Q_BLIF & !MCLK_Q_BLIF # MCLK_Q_BLIF & !N_98_Q_BLIF MCLK_Q_BLIF.C = CKIOX MCLK_Q_BLIF.R = GND Output AND_798 2 Input(s) IORESX, FSX 1 Fanout(s) IRQ0.IR 1 Product Term(s) 1 GLB Level(s) AND_798 = (IORESX & !FSX) Output AND_780 2 Input(s) N_91_Q_BLIF, IORESX 1 Fanout(s) glb03.I11 1 Product Term(s) 1 GLB Level(s) AND_780 = IORESX & !N_91_Q_BLIF Output AND_779 2 Input(s) IORESX, FSX 2 Fanout(s) glb06.I9, glb05.I9 1 Product Term(s) 1 GLB Level(s) AND_779 = (IORESX & !FSX) GLB glb02, B6 7 Input(s) (DOUT.O, DOUTX, I10), (glb02.O2, N_29_Q_BLIF, I14), (glb02.O1, N_30_Q_BLIF, I16), (glb07.O3, N_31_Q_BLIF, I15), (FS.O, FSX, I8), (IORES.O, IORESX, I17), (TXD0.O, TXD0X, I13) 4 Output(s) (N_34_Q_BLIF, O0), (N_30_Q_BLIF, O1), (N_29_Q_BLIF, O2), (N_28_Q_BLIF, O3) 6 Product Term(s) Output N_34_Q_BLIF 4 Input(s) TXD0X, DOUTX, IORESX, FSX 1 Fanout(s) glb07.I3 3 Product Term(s) 1 GLB Level(s) N_34_Q_BLIF.D = FSX & TXD0X # TXD0X & !IORESX # DOUTX & IORESX & !FSX !N_34_Q_BLIF.C = N_47_C N_34_Q_BLIF.R = Output N_30_Q_BLIF 1 Input(s) N_31_Q_BLIF 1 Fanout(s) glb02.I16 1 Product Term(s) 1 GLB Level(s) N_30_Q_BLIF.D = N_31_Q_BLIF !N_30_Q_BLIF.C = N_47_C N_30_Q_BLIF.R = Output N_29_Q_BLIF 1 Input(s) N_30_Q_BLIF 1 Fanout(s) glb02.I14 1 Product Term(s) 1 GLB Level(s) N_29_Q_BLIF.D = N_30_Q_BLIF !N_29_Q_BLIF.C = N_47_C N_29_Q_BLIF.R = Output N_28_Q_BLIF 1 Input(s) N_29_Q_BLIF 1 Fanout(s) glb08.I0 1 Product Term(s) 1 GLB Level(s) N_28_Q_BLIF.D = N_29_Q_BLIF !N_28_Q_BLIF.C = N_47_C N_28_Q_BLIF.R = GLB glb03, B3 3 Input(s) (FS.O, FSX, I8), (IORES.O, IORESX, I17), (glb01.O0, AND_780, I11) 1 Output(s) (N_90_Q_BLIF, O0) 2 Product Term(s) Output N_90_Q_BLIF 3 Input(s) AND_780, IORESX, FSX 1 Fanout(s) glb00.I3 0 Product Term(s) 2 GLB Level(s) N_90_Q_BLIF.D = VCC N_90_Q_BLIF.C = IORESX & !FSX N_90_Q_BLIF.R = !AND_780 GLB glb04, B4 1 Input(s) (glb04.O0, N_98_Q_BLIF, I16) 1 Output(s) (N_98_Q_BLIF, O0) 1 Product Term(s) Output N_98_Q_BLIF 1 Input(s) N_98_Q_BLIF 2 Fanout(s) glb01.I15, glb04.I16 1 Product Term(s) 1 GLB Level(s) N_98_Q_BLIF.D = !N_98_Q_BLIF N_98_Q_BLIF.C = CKIOX N_98_Q_BLIF.R = GLB glb05, B7 2 Input(s) (glb05.O0, N_72_Q_BLIF, I16), (glb01.O2, AND_779, I9) 1 Output(s) (N_72_Q_BLIF, O0) 2 Product Term(s) Output N_72_Q_BLIF 2 Input(s) AND_779, N_72_Q_BLIF 2 Fanout(s) glb06.I7, glb05.I16 1 Product Term(s) 2 GLB Level(s) N_72_Q_BLIF.D = !N_72_Q_BLIF !N_72_Q_BLIF.C = BUF_802 N_72_Q_BLIF.R = !AND_779 GLB glb06, B5 6 Input(s) (glb05.O0, N_72_Q_BLIF, I7), (glb06.O3, N_78_Q_BLIF, I17), (glb06.O2, N_79_Q_BLIF, I16), (glb06.O1, N_80_Q_BLIF, I10), (glb06.O0, N_91_Q_BLIF, I11), (glb01.O2, AND_779, I9) 4 Output(s) (N_91_Q_BLIF, O0), (N_80_Q_BLIF, O1), (N_79_Q_BLIF, O2), (N_78_Q_BLIF, O3) 12 Product Term(s) Output N_91_Q_BLIF 6 Input(s) AND_779, N_78_Q_BLIF, N_91_Q_BLIF, N_72_Q_BLIF, N_80_Q_BLIF, N_79_Q_BLIF 2 Fanout(s) glb01.I11, glb06.I11 2 Product Term(s) 2 GLB Level(s) N_91_Q_BLIF.D = (N_91_Q_BLIF) $ N_72_Q_BLIF & N_78_Q_BLIF & N_79_Q_BLIF & N_80_Q_BLIF !N_91_Q_BLIF.C = BUF_802 N_91_Q_BLIF.R = !AND_779 Output N_80_Q_BLIF 3 Input(s) AND_779, N_72_Q_BLIF, N_80_Q_BLIF 1 Fanout(s) glb06.I10 2 Product Term(s) 2 GLB Level(s) N_80_Q_BLIF.D = N_80_Q_BLIF & !N_72_Q_BLIF # N_72_Q_BLIF & !N_80_Q_BLIF !N_80_Q_BLIF.C = BUF_802 N_80_Q_BLIF.R = !AND_779 Output N_79_Q_BLIF 4 Input(s) AND_779, N_72_Q_BLIF, N_80_Q_BLIF, N_79_Q_BLIF 1 Fanout(s) glb06.I16 3 Product Term(s) 2 GLB Level(s) N_79_Q_BLIF.D = N_79_Q_BLIF & !N_72_Q_BLIF # N_79_Q_BLIF & !N_80_Q_BLIF # N_72_Q_BLIF & N_80_Q_BLIF & !N_79_Q_BLIF !N_79_Q_BLIF.C = BUF_802 N_79_Q_BLIF.R = !AND_779 Output N_78_Q_BLIF 5 Input(s) AND_779, N_78_Q_BLIF, N_72_Q_BLIF, N_80_Q_BLIF, N_79_Q_BLIF 1 Fanout(s) glb06.I17 4 Product Term(s) 2 GLB Level(s) N_78_Q_BLIF.D = N_78_Q_BLIF & !N_72_Q_BLIF # N_78_Q_BLIF & !N_79_Q_BLIF # N_78_Q_BLIF & !N_80_Q_BLIF # N_72_Q_BLIF & N_79_Q_BLIF & N_80_Q_BLIF & !N_78_Q_BLIF !N_78_Q_BLIF.C = BUF_802 N_78_Q_BLIF.R = !AND_779 GLB glb07, A6 4 Input(s) (glb07.O2, N_32_Q_BLIF, I17), (glb07.O1, N_33_Q_BLIF, I16), (glb02.O0, N_34_Q_BLIF, I3), (glb08.O2, N_38_Q_BLIF, I2) 4 Output(s) (N_46_Q_BLIF, O0), (N_33_Q_BLIF, O1), (N_32_Q_BLIF, O2), (N_31_Q_BLIF, O3) 4 Product Term(s) Output N_46_Q_BLIF 1 Input(s) N_38_Q_BLIF 1 Fanout(s) glb00.I12 1 Product Term(s) 1 GLB Level(s) N_46_Q_BLIF.D = N_38_Q_BLIF !N_46_Q_BLIF.C = N_47_C N_46_Q_BLIF.R = Output N_33_Q_BLIF 1 Input(s) N_34_Q_BLIF 1 Fanout(s) glb07.I16 1 Product Term(s) 1 GLB Level(s) N_33_Q_BLIF.D = N_34_Q_BLIF !N_33_Q_BLIF.C = N_47_C N_33_Q_BLIF.R = Output N_32_Q_BLIF 1 Input(s) N_33_Q_BLIF 1 Fanout(s) glb07.I17 1 Product Term(s) 1 GLB Level(s) N_32_Q_BLIF.D = N_33_Q_BLIF !N_32_Q_BLIF.C = N_47_C N_32_Q_BLIF.R = Output N_31_Q_BLIF 1 Input(s) N_32_Q_BLIF 1 Fanout(s) glb02.I15 1 Product Term(s) 1 GLB Level(s) N_31_Q_BLIF.D = N_32_Q_BLIF !N_31_Q_BLIF.C = N_47_C N_31_Q_BLIF.R = GLB glb08, A4 4 Input(s) (glb02.O3, N_28_Q_BLIF, I0), (glb08.O3, N_36_Q_BLIF, I17), (glb08.O1, N_39_Q_BLIF, I16), (glb09.O3, N_40_Q_BLIF, I11) 4 Output(s) (N_44_Q_BLIF, O0), (N_39_Q_BLIF, O1), (N_38_Q_BLIF, O2), (N_36_Q_BLIF, O3) 4 Product Term(s) Output N_44_Q_BLIF 1 Input(s) N_36_Q_BLIF 1 Fanout(s) glb09.I0 1 Product Term(s) 1 GLB Level(s) N_44_Q_BLIF.D = N_36_Q_BLIF !N_44_Q_BLIF.C = N_47_C N_44_Q_BLIF.R = Output N_39_Q_BLIF 1 Input(s) N_40_Q_BLIF 1 Fanout(s) glb08.I16 1 Product Term(s) 1 GLB Level(s) N_39_Q_BLIF.D = N_40_Q_BLIF !N_39_Q_BLIF.C = N_47_C N_39_Q_BLIF.R = Output N_38_Q_BLIF 1 Input(s) N_39_Q_BLIF 1 Fanout(s) glb07.I2 1 Product Term(s) 1 GLB Level(s) N_38_Q_BLIF.D = N_39_Q_BLIF !N_38_Q_BLIF.C = N_47_C N_38_Q_BLIF.R = Output N_36_Q_BLIF 1 Input(s) N_28_Q_BLIF 1 Fanout(s) glb08.I17 1 Product Term(s) 1 GLB Level(s) N_36_Q_BLIF.D = N_28_Q_BLIF !N_36_Q_BLIF.C = N_47_C N_36_Q_BLIF.R = GLB glb09, A2 4 Input(s) (glb09.O2, N_41_Q_BLIF, I16), (glb09.O1, N_42_Q_BLIF, I17), (glb09.O0, N_43_Q_BLIF, I3), (glb08.O0, N_44_Q_BLIF, I0) 4 Output(s) (N_43_Q_BLIF, O0), (N_42_Q_BLIF, O1), (N_41_Q_BLIF, O2), (N_40_Q_BLIF, O3) 4 Product Term(s) Output N_43_Q_BLIF 1 Input(s) N_44_Q_BLIF 1 Fanout(s) glb09.I3 1 Product Term(s) 1 GLB Level(s) N_43_Q_BLIF.D = N_44_Q_BLIF !N_43_Q_BLIF.C = N_47_C N_43_Q_BLIF.R = Output N_42_Q_BLIF 1 Input(s) N_43_Q_BLIF 1 Fanout(s) glb09.I17 1 Product Term(s) 1 GLB Level(s) N_42_Q_BLIF.D = N_43_Q_BLIF !N_42_Q_BLIF.C = N_47_C N_42_Q_BLIF.R = Output N_41_Q_BLIF 1 Input(s) N_42_Q_BLIF 1 Fanout(s) glb09.I16 1 Product Term(s) 1 GLB Level(s) N_41_Q_BLIF.D = N_42_Q_BLIF !N_41_Q_BLIF.C = N_47_C N_41_Q_BLIF.R = Output N_40_Q_BLIF 1 Input(s) N_41_Q_BLIF 1 Fanout(s) glb08.I11 1 Product Term(s) 1 GLB Level(s) N_40_Q_BLIF.D = N_41_Q_BLIF !N_40_Q_BLIF.C = N_47_C N_40_Q_BLIF.R = Clock Input CKIO, Y0 Output CKIOX 2 Fanout(s) glb01.CLK0, glb04.CLK0 Output DIN, IO22 Input (glb00.O2, N_47_Q_BLIF) DIN = N_47_Q_BLIF Input DOUT, IO21 Output DOUTX 1 Fanout(s) glb02.I10 Input FS, IO23 Output FSX 3 Fanout(s) glb01.I8, glb03.I8, glb02.I8 Dedicated Input IORES, I3 Output IORESX 3 Fanout(s) glb01.I17, glb03.I17, glb02.I17 Output IRQ0, IO27 Input (glb01.O3, AND_798) IRQ0 = AND_798 Output MCLK, IO19 Input (glb01.O1, MCLK_Q_BLIF) MCLK = MCLK_Q_BLIF Output RXD0, IO26 Input (glb00.O2, N_47_Q_BLIF) RXD0 = N_47_Q_BLIF Input SCK0, IO24 Output SCK0X 1 Fanout(s) glb00.I7 Input SCLK, IO20 Output SCLKX 1 Fanout(s) glb00.I11 Input TXD0, IO25 Output TXD0X 1 Fanout(s) glb02.I13 Clock Assignments Net Name Clock Assignment N_47_C Internal CLK2 BUF_802 Internal CLK1 CKIOX External CLK0 GLB and GLB Output Statistics GLB Name, Location GLB Statistics GLB Output Statistics GLB Output Name Ins, Outs, PTs Ins, FOs, PTs, Levels, PTSABP glb00, B0 4, 3, 4 BUF_802 1, 2, 1, 1, 1PT N_47_C 3, 5, 2, 1, 4PT N_47_Q_BLIF 1, 2, 1, 1, 1PT glb01, B1 5, 4, 4 AND_779 2, 2, 1, 1, - AND_780 2, 1, 1, 1, 1PT AND_798 2, 1, 1, 1, - MCLK_Q_BLIF 2, 2, 2, 1, 4PT glb02, B6 7, 4, 6 N_28_Q_BLIF 1, 1, 1, 1, 1PT N_29_Q_BLIF 1, 1, 1, 1, 1PT N_30_Q_BLIF 1, 1, 1, 1, 1PT N_34_Q_BLIF 4, 1, 3, 1, 4PT glb03, B3 3, 1, 2 N_90_Q_BLIF 3, 1, 0, 2, - glb04, B4 1, 1, 1 N_98_Q_BLIF 1, 2, 1, 1, 1PT glb05, B7 2, 1, 2 N_72_Q_BLIF 2, 2, 1, 2, 1PT glb06, B5 6, 4, 12 N_78_Q_BLIF 5, 1, 4, 2, 4PT N_79_Q_BLIF 4, 1, 3, 2, 4PT N_80_Q_BLIF 3, 1, 2, 2, 4PT N_91_Q_BLIF 6, 2, 2, 2, - glb07, A6 4, 4, 4 N_31_Q_BLIF 1, 1, 1, 1, 1PT N_32_Q_BLIF 1, 1, 1, 1, 1PT N_33_Q_BLIF 1, 1, 1, 1, 1PT N_46_Q_BLIF 1, 1, 1, 1, 1PT glb08, A4 4, 4, 4 N_36_Q_BLIF 1, 1, 1, 1, 1PT N_38_Q_BLIF 1, 1, 1, 1, 1PT N_39_Q_BLIF 1, 1, 1, 1, 1PT N_44_Q_BLIF 1, 1, 1, 1, 1PT glb09, A2 4, 4, 4 N_40_Q_BLIF 1, 1, 1, 1, 1PT N_41_Q_BLIF 1, 1, 1, 1, 1PT N_42_Q_BLIF 1, 1, 1, 1, 1PT N_43_Q_BLIF 1, 1, 1, 1, 1PT Maximum-Level Trace GLB Level, Name, Ins GLB Output Name 2, glb03, 3 N_90_Q_BLIF 1, glb01 AND_780 2, glb05, 3 N_72_Q_BLIF 1, glb01 AND_779 2, glb06, 7 N_91_Q_BLIF 1, glb01 AND_779 2, glb06, 4 N_80_Q_BLIF 1, glb01 AND_779 2, glb06, 5 N_79_Q_BLIF 1, glb01 AND_779 2, glb06, 6 N_78_Q_BLIF 1, glb01 AND_779 Pin Assignments Pin Name Pin Assignment Pin Type, Pin Attribute IORES 2 Dedicated Input, PULLUP SCK0 3 Input, PULLUP TXD0 4 Input, PULLUP RXD0 5 Output, PULLUP IRQ0 6 Output, PULLUP CKIO 11 Clock Input MCLK 40 Output, CRIT, PULLUP SCLK 41 Input, PULLUP DOUT 42 Input, PULLUP DIN 43 Output, PULLUP FS 44 Input, PULLUP Design process management completed successfully