Setup and Hold Report:
---------------------

Design Name: AND_FF
Part Name: ispLSI1016E-80LJ44

  This report lists the setup/hold requirements for all the boundary
  registers in the design


Required Setup and Hold

  Register Name         Data                Clock               Setup(ns)      Hold(ns)
==-------------------------------------------------------------------------------------
  GLB_...BLIF *1        TXD0                SCLK                -3.10          6.90
  GLB_...BLIF *1        TXD0                SCK0                -2.90          6.70
  GLB_...BLIF *1        FS                  SCLK                -2.80          6.80
  GLB_...BLIF *1        FS                  SCK0                -2.60          6.60
  GLB_...BLIF *1        DOUT                SCLK                -3.10          6.90
  GLB_...BLIF *1        DOUT                SCK0                -2.90          6.70
  GLB_...BLIF *1        IORES               SCLK                -2.70          6.70
  GLB_...BLIF *1        IORES               SCK0                -2.50          6.50
==-----------------------------------------------------------------------------------

Index Name Table
==----------------------------------------
    *1  GLB_N_34_Q_BLIF
==----------------------------------------