Tco Path Report:
-----------------

Design Name: AND_FF
Part Name: ispLSI1016E-80LJ44
   This report lists all the path delays from a primary input
   that drives the Clock input of a register, whose Q output
   drives a primary output

 Tco Path Definition:
 Tco =  Maximum delay from primary input to register clock_pin
      + Maximum delay of register  clock-to-Q
      + Maximum delay from register Q_output to primary output


Tco Paths:

  Register            Source              Destination              Path Delay
  Name                Reference Clock     Primary Output             [ns]
==----------------------------------------------------------------------------------
  GLB_...BLIF *1      SCLK                DIN                      20.70
  GLB_...BLIF *1      SCLK                RXD0                     20.70
  GLB_...BLIF *1      SCK0                DIN                      20.50
  GLB_...BLIF *1      SCK0                RXD0                     20.50
  GLB_...BLIF *2      CKIO                MCLK                     7.00
==--------------------------------------------------------------------------------

Index Name Table
==----------------------------------------
    *1  GLB_N_47_Q_BLIF
    *2  GLB_MCLK_Q_BLIF
==----------------------------------------